Memory element, stacking, memory matrix and method for operation

ABSTRACT

Disclosed is a memory element, a stack, and to a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V 0 , this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V 1 , it can be transferred into the likewise high-impedance state 1. By applying a read voltage V R , the magnitude of which is smaller than the write voltages V 0  and V 1 , the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.

This is a Divisional Application of U.S. Ser. No. 13/261,044 filed Dec.9, 2011.

The invention relates to a memory element, a stack and a memory matrixin which this memory element can be used, to methods for operating thememory element, the stack and the memory matrix, and to a method fordetermining the truth value of a logic operation comprising memoryelements.

BACKGROUND OF THE INVENTION

Charge-based memories, such as flash memories, are close to reaching thephysical limits of miniaturization. Due to their complexity, they takeup more area than the ideal 4F², with a given minimal feature size F. Inaddition, the minimal feature size F itself is limited. Memories basedon passive, resistively switching memory cells can be achieved on anarea of 4F², and a minimal feature size F of less than 10 nm istechnically feasible.

A large number of memory cells are typically combined in a memory matrixcomprising intersecting busbars called word lines and bit lines. Exactlyone memory cell is connected between one word line and one bit line inevery case to enable the individual addressing thereof by controllingthe word line and the bit line.

In this design, when purely passive, resistive memory cells are usedbetween a word line and a bit line, there is not only the direct currentpath through the addressed memory cell, but also, disadvantageously,parasitic current paths through further memory cells, word lines and bitlines. Considerable power loss occurs, and since the configuration ofthe parasitic current paths is dependent upon the bit patterns stored inthe memory matrix, the reliability of the memory suffers.

To interrupt each parasitic current path at least at one point, it isknown to provide a memory element as a series circuit comprising amemory cell and a nonlinear component such as a diode.Disadvantageously, only unipolar resistively switched memory cells canbe used in such a circuit, since the nonlinear component specifies apreferred direction. The problem of parasitic current paths is merelyreplaced by the problem that unipolar switching memory cells requirehigh voltages for switching. In turn, the resulting high currents bringabout a high power loss and diminish the scaling properties. Inaddition, adequately miniaturized diodes that can carry the requiredcurrent densities have not been available.

SUMMARY OF THE INVENTION

The object of the invention is therefore that of providing a memoryelement that acts as a high-impedance resistor in the parasitic currentpaths occurring in a memory matrix, without in principle being limitedto unipolar switching. A further object of the invention is that ofproviding a method with which an array comprising memory elements can beturned into a gate for logic operations.

These objects are achieved according to the invention by a memoryelement according to the main claim, a stack containing this memoryelement, a memory matrix containing this memory element or this stack,by a method for operating the memory element, the stack or memory matrixaccording to alternative independent claims, and by a method fordetermining the truth value of a logic operation according to a furtheralternative independent claim. Further advantageous embodiments willbecome apparent from the back-referenced dependent claims.

A memory element was developed within the scope of the invention, whichhas at least a first stable state 0 and a second stable state 1. Thismemory element can be transferred into the state 0 by applying a firstwrite voltage V₀, and into the state 1 by applying a second writevoltage V₁. The two states 0 and 1 differ in that the memory elementexhibits different electrical resistance values upon application of aread voltage V_(R), the magnitude of which is less than the writevoltages V₀ and V₁.

According to the invention, the memory element comprises a seriescircuit having at least two memory cells A and B which have,respectively, a stable state A0 and B0 having higher electricalresistance, and a stable state A1 and B1 having lower electricalresistance.

It was recognized that this series circuit distributes a voltage V₀, V₁or V_(R) applied to the memory element to the two memory cells A and Bin the sense of a voltage divider. As a result, the two memory cells Aand B can be influenced independently of one another, provided they arein different states. For instance, if the memory cell A is in the stateA0 and the memory cell B is in the state B1, the larger portion of theapplied voltage drops across the memory cell A. By applying a voltage,the memory cell A can then be switched into the state A1, without thevoltage applied therefor by way of the entire memory element and,therefore, by way of the series connection of the cells A and B,changing the state of the cell B.

It was recognized that a single memory element can be addressedspecifically using this type of connection, especially in a matrixcomprising a plurality of memory elements, without changing the statesof other memory elements. In such a matrix it is typically impracticalto provide a separate current circuit for every individual memoryelement. Instead, every memory element is typically connected between afirst busbar (typically referred to as a word line) and a second busbar(typically referred to as a bit line), to which the many further memoryelements are connected in each case. A given word line and a given bitline are interconnected directly by way of only one memory element,thereby making it possible to address this memory element individuallyby applying a voltage between this word line and bit line. However, acurrent can also flow on parasitic alternate routes by way of furthermemory elements and, therefore, by way of further word lines and bitlines between the word line and the bit line between which the voltageis applied. As a disadvantage, these further memory elements aretherefore also acted upon by a voltage. The voltage divider comprisingthe memory cells A and B, which is provided according to the invention,has the effect in such a matrix of advantageously increasing the safetymargin between the minimum voltage, which is required to switch a memoryelement, and the voltage at which further memory elements areunintentionally switched to the stated parasitic paths.

It was also recognized that the memory element according to theinvention acts as a high-impedance resistor whenever at least one of thememory cells A or B is in the state A0 or B0, respectively. In three ofthe four combinations of states that can be achieved in the seriescircuit (A0 and B1, A1 and B0, A0 and B0), the total resistance of thememory element is therefore high. Therefore, there are distinguishablestates in the memory element, which can be used to store a bit ofinformation, and in each of which the total resistance is high. Thememory element can therefore function as a high-impedance resistor inparasitic current paths, independently of whether a 0 or a 1 is storedtherein at the time. Each of the memory cells can also be designed forbipolar switching. The fundamental limitation to unipolar switchingmemory cells resulting from the series connection comprising a memorycell and a nonlinear component known from the prior art is thuseliminated.

In a particularly advantageous embodiment of the invention, the memorycells A and B are interconnected in a manner such that the state 0 ofthe memory element is coded in the combination of states A1 and B0, andthe state 1 of the memory element is coded in the combination of statesA0 and B1. This has the effect that the memory element has high totalresistance in both states. If the memory element is in the restingstate, and therefore a lower voltage drops thereacross than the readvoltage V_(R) required for reading, this voltage only results in a verylow leakage current. As a result, in a memory matrix comprising aplurality of memory elements in particular, the unwanted leakage currentis delimited by parasitic current paths.

In a further particularly advantageous embodiment of the invention, thememory cells A and B and the read voltage V_(R) are dimensioned suchthat the read voltage V_(R) sets the state A1 and leaves the state ofthe memory cell B unchanged.

In this embodiment, if the memory element is in the state 0, this readvoltage V_(R) does not change anything about the state of the memorycells because the memory cell A is already in the state A. Therefore,the electrical resistance likewise does not change. It is dominated bythe memory cell B located in the state BO and therefore remains high.

However, if the memory element is in the state 1, the memory cell A isswitched by the read voltage V_(R) from the state AO into the state A1and, therefore, into the state having lower electrical resistance. Sincethe memory cell B is in the state B1 and, therefore, likewise in thestate having the lower electrical resistance, the total resistance ofthe memory element is low. The combination of the states A1 and B1 ofthe memory cells is the ON state of the memory element. In this manner,upon application of the read voltage V_(R), the states 0 and 1 of thememory element can be distinguished from one another. Reading a state 1is destructive, i.e. after the readout, the memory element does notautomatically return to the state that existed before the readout. Thememory element can be transferred back to the state 1 by applying thewrite voltage V₁.

The memory cells A and B can also be located in the combination ofstates A0 and B0. This typically occurs only before the first use of thememory element.

By applying the write voltage V₀ or V₁, the memory element can beinitialized out of this state into one of the states 0 or 1,respectively, provided for storage. In particular, all memory elementscan be initialized in a memory matrix in this manner before the initialuse.

It was recognized that, in this embodiment of the memory element, in amatrix comprising a plurality of memory elements, the current flowthrough parasitic current paths between the word line and the bit lineacted upon by the read voltage V_(R) can be advantageously minimized. Anadequately high portion of the read voltage V_(R) drops only at thememory cell A of the directly addressed memory element, in order tooptionally switch this memory cell from the state A0 into the state A1.Along every unwanted parasitic path through a plurality of furthermemory elements, however, only a portion of the read voltage V_(R) dropsacross every individual memory element, which is inadequate forswitching the particular memory cell A into the state A1. Therefore, theapplication of the read voltage V_(R) opens only one path having lowresistance between the word line and the bit line, between which it wasapplied, provided the memory element connected between this word lineand this bit line is located in the state 1. The electrical resistanceof all other memory elements on parasitic paths remains high in thiscase.

Advantageously, the write voltages V₀ and V₁ have different signs. Thiscan be achieved, in a further particularly advantageous embodiment ofthe invention in particular, in that the memory cells A and B areantiserially connected. Due to the write voltages V₀ and V₁ havingdifferent signs, there is no longer a need to provide a great distancebetween the write voltages V₀ and V₁ with regard to the magnitudesthereof, in order to still be able to reliably distinguish between theeffects thereof on the memory element, even with consideration for thetechnical tolerances. In particular, the write voltages V₀ and V₁ can beopposite and equal. They are therefore separated by a distance equal totwice their magnitudes, thereby advantageously making it possible tomake the amount smaller.

If the memory cells A and B are antiserially connected, the applicationof the write voltage V₀ or V₁ brings about the simultaneous orquasi-simultaneous transfer of the memory cells A and B into therespective opposite states, i.e. into A0 and B1 or A1 and B0. These arethe two stable states 1 and 0 of the memory element.

The invention therefore relates in general to a resistive memory elementthat is embodied as a passive resistive memory element. This memoryelement comprises two at least functionally identical resistive memorycells A and B which are connected in series in a current path and areoriented antiparallel to one another in this current path. The memorycells A and B are therefore antiserially connected. “Passive” means thatthe memory element contains no further active switching elements apartfrom the active material in the memory cells A and B. In particular, thecurrent path through the memory cells A and B can form the passivememory element.

Different signs of the write voltages V₀ and V₁ are achieved inparticular when the memory element is designed as a bipolar switchingmemory element. This can be achieved, for example, by forming the memorycells A and B out of a linear bipolar resistively switching material.Such materials are, for example, silicon dioxide, methylsilsesquioxane,methylated-hydrogenated silsesquioxane, tungsten oxide (in particulartungsten(VI) oxide, WO₃), germanium selenide, titanium dioxide orstrontium titanate. Advantageously, therefore, at least one of thememory cells A or B contains at least one material from this group asthe active material having a changeable electrical resistance.

The lower the voltages are that are applied to the resistive memorycells, the lesser the current is that is driven through the memory cellsby this voltage, and the lower the power consumption is duringoperation. Lower energy consumption is associated with reduced thermalload on the memory element and, therefore, improved service life. Inaddition, the minor irreversible damage that a memory cell incurs withevery transfer procedure depends greatly on the magnitude of the writevoltage. At a lower write voltage, the memory cell withstands a muchgreater number of transfer processes. In flash memories according to theprior art, which forcibly drive charges with high write voltages up to10 V through a barrier, the damage caused by writing is atechnologically limiting factor. Successive losses of memory cells arenormal to an extent such that the controller used for control requiresfunctionalities to manage these losses.

If the memory element is now designed as a bipolar switching memoryelement, for example, lower absolute write voltages are required thanfor unipolar switching memory elements. Therefore, a lower current isdriven through the memory element. The power loss is thereforediminished and the memory element can be more easily scaled.

The memory cells A and B advantageously have nominally equal resistancevalues in the states A0 and B0, and A1 and B1, respectively. The totalresistance of the memory element in the two states 0 and 1 is thenexactly equal, provided only a voltage less than the read voltage V_(R)is present across the memory element. Deviations from this nominalresistance value can be used for diagnosis to enable early detection ofan emerging failure of the memory element. It is then possible, forexample, as is common in flash memories, to transfer the informationinto a reserve memory element and hide the failing memory element asdefective.

Advantageously, the memory cells A and B are dimensioned such that theelectrical resistance of at least one of the memory cells A and Bchanges upon transition from the state A0 into the state A1 or from thestate B0 into the state B1 by a factor between 10 and 10⁸, preferablybetween 10² and 10⁶ and particularly preferably between 10³ and 10⁸. Thegreater the change in resistance in the memory cells is, the greater thesignal distance is in the resistance exhibited when the read voltageV_(R) is applied between the states 0 and 1 of the memory element.

In a particularly advantageous embodiment of the invention, the memoryelement is in the form of a stack comprising a first metallic,semiconductive or conductive oxidic electrode, a first layer of activematerial having a changeable electrical resistance, a second metallic,semiconductive or conductive oxidic electrode, a further layer of activematerial having a changeable electrical resistance and a third metallic,semiconductive or conductive oxidic electrode. The first layer of activematerial then forms the memory cell A, and the second layer of activematerial forms the memory cell B. The active materials of the memorycells A and B can be identical or different. For example, the electrodescan each be made of platinum, and the active material can be TiO₂ ineach case. Such a configuration as a stack can be integratedparticularly well into existing processes of mass production ofresistive memories. Basically, any bipolar switching material systemsuch as a solid electrolyte can be used. The effect of this embodimentis not tied to the electrodes and layers of active material beingdisposed one above the other in a stack. It is sufficient for the memoryelement to comprise two electrodes which connect an array of two memorycells with the outside world, and for a further electrode to be disposedbetween these two electrodes.

In an advantageous embodiment of the invention, at least the metal ofthe second electrode differs from the material of the first and/or thethird electrode. In particular, at least the metal of the secondelectrode can be more unreactive or reactive than the metals of thefirst and the third electrode. For example, the first and the thirdelectrode can be made of copper, and the second electrode can be made ofplatinum. The difference in the reactivities of the electrodes thendefines the polarities of the write voltages. Moving from the first tothe second metallic electrode, the reactivity gradient extends in adifferent direction than moving from the second to the third electrode.The memory cells A and B are therefore antiserially connected.Optionally, the second electrode in the interior of the stack can beacted upon by a bias voltage. Using such a bias voltage, thecurrent-voltage characteristic curve of the memory element can besymmetrized if the active material of one or both of the memory cellshas a current-voltage characteristic curve that is not symmetrical aboutthe origin.

Advantageously, at least one of the electrodes contains a material fromthe group Au, Cu, Ag, Pt, W, Ti, Al, Ni, TiN, Pd, Ir, Os, IrO₂, RuO₂,SrRuO₃, and polycrystalline silicon.

One or more electrodes can also be made of an electrically conductiveoxide. This can be an originally conductive metal oxide, for example, oran initially insulating oxide that was made conductive by way ofsubsequent doping. Electrodes made of an electrically conductive oxideare advantageous, for example, when the active material belongs to thesame material class. It is then possible to use similar or evenidentical techniques to manufacture the electrodes and the activematerial. Ideally, this enables the electrodes and the active materialto be deposited onto a substrate one after the other in situ, withoutinterrupting the vacuum. For example, electrodes and active material canbe made of one and the same starting material simply by using differentdeposition parameters.

In a further advantageous embodiment of the invention, at least one ofthe memory cells A or B comprises two electrodes, on the common boundarysurface of which a zone having a changed charge carrier concentrationforms, as the active material. This zone can be a depletion zone or aSchottky barrier. For example, the material of one electrode can be adoped ternary metal oxide, and the material of the other electrode canbe a metal. An example of a doped ternary metal oxide is niobium-dopedSrTiO₃. A zone which acts as an active material forms on the commonboundary surface comprising an electrode made of platinum.

This embodiment of the invention has the advantage that the memory cellstill comprises only two layers. The manufacture of epitaxial layersystems is becoming overproportionally more difficult as the number ofindividual layers increases, due to lattice maladjustments.

In a further advantageous embodiment of the invention, a furtherresistor R is connected in series with the memory cells A and B, or isinserted into at least one of the memory cells A and/or B. It is thenpossible to also use memory cells A and/or B, the positive and negativeswitching thresholds of which are different magnitudes. The resistor Rmatches the switching thresholds to one another with regard tomagnitude. It becomes active only in the state in which both memorycells A and B are each in the state of low electrical resistance, i.e.the combination of states A1 and B1 is present. Advantageously, it isdimensioned such that, in this combination of states, the same voltagedrops across each of the two memory cells A and B. Installing theresistor into one of the memory cells A and/or B saves the space for aseparate resistor and is technically particularly easy to achieve. Ifthe memory elements are manufactured, e.g. by depositing a series ofthin layers, it is then only necessary to place only one furthermaterial into the sequence of layers, as the resistor layer.

If one of the memory cells has positive and negative switchingthresholds, the magnitudes of which differ very greatly, and this is notcompensated for at least partially by the resistor R, it is possible forthe case to occur in which, starting at the combination of states A0 andB1 (state 1 of the memory element), the minimally required read voltageV_(R) already switches the memory cell B into the state B0 and thereforeacts simultaneously as the write voltage V₀. The memory element does notthen reach the combination of states A1 and B1 (the ON state of thememory element) provided according to the invention as the signal forthe presence of the state 1.

If the memory element is part of a memory matrix, the resistor R canalso be disposed outside of the memory element itself, in particular. Itcan be located in one of the leads, for instance, by way of which theword lines and/or bit lines of the memory matrix are controlled. Asingle resistor R is then sufficient for the entire memory matrix. If aplurality of memory elements is to be addressed simultaneously, it isadvantageous to provide one resistor for each row or column of thememory matrix. The drain-source resistor or collector-emitter resistorof the transistor used to control the memory matrix can be used as theresistor, for example.

Advantageously, in this case, at least one of the memory cells containsan ion-conducting material, and particularly GeSe, TiO₂, WO, or MSQ(methylsilsesquioxane). By using these materials, it was possible toachieve agreement between the theoretically expected and theexperimentally observed switching behavior in the studies conducted bythe inventors.

In general, the active material can advantageously contain at least onematerial from the group Ge_(x-)Se_(1-x) TiO_(x), SiO_(x) (in particularSiO₂), CuO_(x), ZnO_(x), ZrO_(x), NiO_(x), HfO_(x), WO_(x) (inparticular tungsten(VI) oxide, WO₃), Si₃N₄, SrZrO₃:Cr,Ba_(1-x)Sr_(x)TiO₃ (in particular SrTiO₃), MSQ (methylsilsesquioxane ormethylated-hydrogenated silsesquioxane), HSQ (hydrogen silsesquioxane),Cu:TCNQ (copper:tetracyanoquinodimethane), (Pr,Ca)MnO₃, (La,Ca)MnO₃,Cu₂S, Ag₂S, (Zn,Cd)S, Al₂O₃, FeO, CoO, MnO₂, In₂O₃, Ta₂O₅, Nb₂O₅ andVO₂.

The active material can be a dielectric which normally insulates. Byapplying a sufficiently high voltage, at least one inner path can beformed in the material along which it becomes conductive. This path canbe formed by different mechanisms, such as defects, metal migration andfurther effects. If the conducting path has been formed once, it can beinterrupted, whereby the electrical resistance of the active material isincreased, and it can be restored, whereby the electrical resistance isdiminished. The resistance values can be adjusted by the applied voltageor by changing an adjacent boundary surface.

The invention also relates to a stack comprising at least two memoryelements P and Q. In this stack, a pole of the memory element P isconnected to a pole of the memory element Q by way of an electricalcontact O that is accessible for an external connection. Such a stackincreases the integration density. This, thereby makes it technicallyfeasible for each of the memory elements according to the inventioncontained therein to essentially be a high-impedance resistor. This islow-impedance when, and only when, it has been transferred from thestate 1 into the ON state by application of the read voltage V_(R). As aresult, parasitic current paths and high static power losses accompaniedby heating are advantageously prevented.

Since the contact O is now accessible for an external connection, bothmemory elements P and Q can be acted upon independently of one anotherwith voltages having the same or different polarities. If the contact Ois at ground potential (GND), for example, the other pole of the memoryelement P can be brought to a positive or negative potential. A voltagedrop across the memory element P can therefore be set, which acts onthis memory element as write voltage V₀, as well as one that acts aswrite voltage V₁. It does not depend, therefore, on the absolutepotential level in each case, but rather on the potential differencebetween the two poles of the memory element P. The same applies for thememory element Q.

The memory elements can also be acted upon, together with write voltagesor read voltages, in the series circuit in which they are located in thestack.

As explained above in the discussion of the individual features of thememory element according to the invention, the advantages of themeasures according to the invention are exhibited in particular in amemory matrix comprising a plurality of memory elements or stacks. In anadvantageous embodiment of the invention, the memory element istherefore adapted to the use in the memory matrix of a resistive workingmemory (RRAM). The invention therefore also relates to the use of thememory element in the memory matrix of a RRAM.

Within the scope of the invention, a memory matrix comprising a largenumber of word lines, in the form of tracks, and bit lines intersectingtherewith, was developed. The word lines and/or the bit lines can, inparticular, extend parallel to one another.

In an advantageous embodiment of the invention, each word line and eachbit line intersect at one location at most. In particular, the wordlines can be disposed on a first plane and the bit lines can be disposedon a second plane. The memory matrix differs from memory matrices of thetype in question in that memory elements according to the invention orstacks thereof are located at intersections of word lines and bit lines.Advantageously, the word line and the bit line are conductivelyconnected at each intersection with at most one memory element or onestack. Particularly advantageously, at most one memory element or onestack is connected between the word line and the bit line at eachintersection. The word lines and/or the bit lines can advantageouslyfunction simultaneously as electrodes of the memory element or thestack. The size F in the memory matrix is advantageously 10 nm or less.

It was recognized that the embodiment according to the invention of thememory element as voltage divider comprising two, preferablyantiserially connected memory cells eliminates substantial disadvantagesof memory matrices of the type in question. According to the prior art,when a memory element is read from or written to, a current flows notonly through the memory element currently being addressed by way of theselected word line and bit line, but also through parasitic currentpaths comprising a plurality of further memory elements, word lines andbit lines. These parasitic leakage currents are minimized in that eachmemory element is basically in a state having high electrical resistanceunless this individual memory element is currently being acted upon bythe read voltage V_(R). According to the prior art, leakage currentsthrough parasitic current paths were the limiting factor for the size ofmemory matrices of the type in question.

Since the non-addressed memory elements are essentially high-impedance,the electrical properties of the memory matrix according to theinvention no longer depend on the bit patterns that were written, incontrast to the memory matrices of the type in question. This dependenceon bit pattern made it difficult, according to the prior art, to readout memory matrices of the type in question, and made correct readingimpossible in many cases.

The memory matrix can be used within the framework of a hybrid CMOStechnology.

In principle, the memory matrix can also have a three-dimensionalconfiguration, and thus memory elements according to the invention arestacked one above the other therein.

For the CMOS integration of the memory matrix according to theinvention, it is advantageous that the resistance of the memory elementscontained in this memory matrix are no longer dependent upon the bitpatterns stored in the matrix. The CMOS electronics used to control thememory matrix then no longer need to be designed to allow the totalresistance of the memory matrix to vary in a wide range.

The memory elements according to the invention function particularlyadvantageously in the embodiment of the invention, in which the memorymatrix comprises stacks of memory elements. In the final analysis, it isthereby possible to obtain a three-dimensional memory matrix. In thiscase it is particularly advantageous that the interior of this memorymatrix is free of transistors. Transistors require a lot of space andinduce high power losses. The size of an approximately cube-shaped arraycomprising transistor-based memory elements rapidly reaches limits dueto the inadequate heat dissipation from the center of the cube. Theselimits are markedly expanded by the memory elements according to theinvention.

The memory matrix can be used in a resistive working memory (RRAM) inparticular, where it combines the high integration density and accesstime of DRAM with the non-volatility of flash memories. The inventiontherefore also relates to a resistive working memory (RRAM) comprisingat least one memory matrix according to the invention. The memory matrixcan be a passive memory matrix in particular, which contains onlypassive memory elements. It is then possible to eliminate all activeelements that are controllable independently of the currents through theword lines and bit lines within the memory matrix. A RRAM contains, inaddition to the memory matrix itself, external control electronics forthe memory elements which can be embodied in CMOS technology, forexample. A decoder can be provided for the selective control of the wordlines, and a further decoder can be provided for the selective controlof the bit lines, for example.

Within the scope of the invention, a method for operating the memoryelement according to the invention, the stack according to theinvention, or the memory matrix according to the invention wasdeveloped. This method is characterized in that a read voltage V_(R) isapplied to at least one memory element, the magnitude of which isgreater than a first threshold value required to transfer one of thememory cells A or B of the memory element from the state A0 or B0 intothe state A0 or B0, respectively, wherein the read voltage V_(R) islower, with regard to magnitude, than a second threshold value requiredto transfer the other memory cell A or B of the memory element from thestate A0 or B1 into the state A0 or B0, respectively.

Alternatively or in combination therewith, a further method foroperating the memory element according to the invention, the stackaccording to the invention, or the memory matrix according to theinvention, which was developed within the scope of the invention, can beused. This method is characterized in that the information read out byapplying the read voltage V_(R) to a memory element is subsequentlyre-stored in the memory element. Provided the application of the readvoltage V_(R) induces a change in the total resistance of the memoryelement, the memory element does not automatically return to the statethat existed before the application of the read voltage V_(R). Thereadout is therefore destructive. This applies especially to theembodiment of the memory element, in which the state 0 of the memoryelement is coded in the combination of the states A1 and B0, and inwhich the state 1 of the memory element is coded in the combination ofthe states A0 and B1. After a 1 is read out, the combination A1 and B1is present, which does not correspond to either of the two definedstates 0 and 1 of the memory element. The state 1 is restored bysubsequently applying the write voltage V₁ which returns the memory cellA into the state A0.

Alternatively or in combination therewith, the invention also relates toa further method for operating a memory element, a stack or a memorymatrix. As a result of this method, upon application of the writevoltage V₀ and/or V₁, the time characteristic of the current driventhrough the memory element, through the stack, or through the memorymatrix, is evaluated.

This method offers special advantages when the memory element is in theembodiment in which the state 0 of the memory element is coded in thecombination of the states A1 and B0, and in which the state 1 of thememory element is coded in the combination of the states A0 and B1.

It was recognized that the transfer of the memory element from the state0 into the state 1, or vice versa, then takes place essentially in aplurality of steps, by applying the corresponding write voltage. In thestate 0 and in the state 1 of the memory element, one of the memorycells is always in the state A0 or B0, respectively, and the othermemory cell is in the state A1 or B1, respectively. If that writevoltage is applied to the memory element as a series circuit of bothmemory cells, which is suitable for switching the memory element intothe state that is not present, this write voltage initally dropssubstantially across that memory cell that has the higher electricalresistance, i.e. is therefore in the state A0 or B0. As a result, thismemory cell is switched into the state A1 or B1. Both memory cells arenow in the state A1 or B1, and the memory element is therefore in the ONstate. This state has a short duration, however. The write voltage nowdrops evenly across both memory cells A and B. Now more voltage dropsacross those memory cells that were in the state A1 or B1 beforeapplication of the write voltage than at the beginning of the writeprocess. It is therefore switched into the state A0 or B0 by the portionof the write voltage dropping thereacross. Finally, both memory cellshave changed their state, and the memory element as a whole is in one ofthe two states 0 (combination A1 with B0) or 1 (combination A0 with B1).

During the short time period between the switchover of the first memorycell and the switchover of the second memory cell, the memory element isin the ON state, i.e. in a state having low electrical resistanceoverall. This becomes noticeable in that the write voltage drives a highcurrent pulse through the memory cell during this time period. Theinventors recognized that an evaluation of the time characteristic ofthe current, i.e. an evaluation of this pulse can be utilized inmultiple ways in the operation of the memory element, the stack or thememory matrix.

In a particularly advantageous embodiment of the invention, theoccurrence of a short pulse in the current driven through the memoryelement, through the stack or through the memory matrix can be evaluatedas confirmation of a successful switchover process. Theoretically, apulse duration of less than 1 ps is sufficient therefor. Pulse durationsof 10 ns or less for TiO₂ and pulse durations of 5 ns or less for WO₃,as the active material of the memory cells, have been demonstrated inpractical application. For all active materials tested by the inventors,pulse durations of 10 ns or less are exhibited in the transferprocesses.

The state change of the two memory cells is confirmed by the occurrenceand subsequent decay of the pulse. The pulse occurs only when the firstmemory cell is successfully switched into the state A1 or B1, and thememory element as a whole transfers into the ON state. It decays only ifthe second memory cell is subsequently switched into the state A0 or B0and the memory element as a whole therefore assumes a ON state, oncemore having a high electrical resistance. If an increased current is notdriven through the memory element by a write voltage which would besuitable for a transfer of the memory element into the state that is notcurrently present, or if it does not decay, the memory element isdefective.

Alternatively or in combination therewith, the occurrence of the pulsecan be used as information about the state of the memory element thatexisted before the application of the write voltage. For example, if thewrite voltage V₁ is applied, then only one pulse occurs if the memoryelement was in the state 0 before the application of this write voltage.In contrast, if the state 1 was present, the write voltage V₁ dropssubstantially across the memory cell A located in the state A0 since thememory cell B is in the state B1 and is therefore low-impedance. Now,however, the write voltage V₁ does not have the correct polarity toswitch the memory cell A into the state A1. Both memory cells A and B,and therefore also the memory element as a whole, do not change theirstate, and therefore a pulse does not occur.

In this manner, upon writing with the write voltages V₀ and V₁, it issimultaneously possible to also read out the information already presentin the memory element. It is advantageous that a separate voltage sourcefor a read voltage V_(R) is not required. In the simplest case, theground potential (GND) and, differing therefrom, a potential V of asingle voltage source are all that is additionally required foroperation. The polarity with which these two potentials are applied tothe two poles of the memory element determines whether the memoryelement is acted upon by the write voltage V₀ or by the write voltageV₁.

In a further advantageous embodiment of the invention, a change in thetime characteristic of the current driven through the memory element,through the stack or through the memory matrix is evaluated in repeatedwrite cycles as an indicator that degradation of a memory element hasbegun. In a memory matrix comprising a large plurality of memoryelements in particular, this memory element or a limited region in thememory matrix in which this memory element is located can be marked asdefective and blocked for further accesses.

The more memory elements a memory matrix contains, and the smaller thesememory elements are, the greater the likelihood is that one or more ofthe memory elements will fail after a certain number of write cyclessimply due to the variabilities in the manufacturing process. The effectof a statistically occurring defect in a layer of a memory cell istherefore markedly greater when this layer comprises only 100 atoms thanwhen it comprises 10,000 atoms.

In an advantageous embodiment of the invention, the write voltages V₀and/or V₁ and/or the read voltage V_(R) are each applied, in part, byway of the word line and by way of the bit line. In particular, half ofthe voltage can be applied by way of the word line, and half by way ofthe bit line. This voltage pattern (1/2-pattern) advantageously reducesthe voltages that are applied to the memory element not addressed by wayof the selection of the word line and the bit line. A furtheradvantageous embodiment of the invention aims for the same effect.According to this embodiment, upon application of the write voltages V₀and/or V₁ and/or the read voltage V_(R) to a memory element, a voltagehaving the opposite sign is applied to at least one further memoryelement. In particular, countervoltages having a magnitude that is 2/3that of the voltage applied to the addressed memory element can beapplied to all non-addressed word lines, and countervoltages having amagnitude that is 1/3 that of the voltage applied to the addressedmemory element can be applied to all non-addressed bit lines. Thecountervoltage having the opposite sign, which is applied within theframework of this voltage pattern (2/3-pattern), compensates at least inpart for the influencing of non-addressed memory elements by the voltageV₀, V₁ and V_(R) applied to the addressed memory element.

The invention also relates to a method for determining the truth valueof a logic operation of two variables K and L in an array comprising atleast two memory elements P and Q, each of which has at least one stablestate 0 and one stable state 1, which can be transferred into the state0 by application of a first write voltage V₀, and into the state 1 byapplication of a second write voltage V₁.

Advantageously, the two states 0 and 1 of the memory elements P and Qbecome manifest in different electrical resistance values of the memoryelements P and Q upon application of a read voltage V_(R), the magnitudeof which is smaller than the write voltages V₀ and V₁. Preferably,memory elements P and Q having nominally identical write voltages V₀, V₁and read voltages V_(R) are selected.

The variables K and L are each embodied in the form of two voltagelevels which are assigned to the truth values 0 and 1, wherein thedifference between the two voltage levels, with regard to magnitude, isat least as great as the write voltages V₀ and V₁ of the memory elementsP and Q. Advantageously, at least one of the voltage levels is at leastas great, with regard to magnitude, as the write voltages V₀ and V₁ ofthe memory elements P and Q. For example, the ground potential (GND) canbe assigned to the truth value 0, and a voltage level V which is greaterthan the write voltages V₀ and V₁ of the memory elements P and Q, withregard to magnitude, can be assigned to the truth value 1.

According to the invention, at least one of the two poles P₁, P₂ of thememory element P is acted upon by the voltage level of the variable K.At least one of the two poles Q₁, Q₂ of the memory element Q is actedupon by the voltage level of the variable L. Advantageously, both memoryelements P and Q are first initialized in a defined state, such as 0.

It was recognized that, by way of these measures, the truth value of thelogic operation of the variables K and L can be stored in the states ofthe memory elements P and Q, and can be read out of these memoryelements.

Therefore, in the simplest form, for example, the result of theoperation “K OR L” can be stored by switching the memory element Pbetween the voltage level of the variable K and ground (or anotherfreely selectable potential) and the memory element Q between thevoltage level of the variable L and ground (or another freely selectablepotential).

If the variable K has the truth value 1, the memory element P isswitched into the state 1 by way of the corresponding voltage level. Ifthe variable L has the truth value 1, the memory element Q is switchedinto the state 1 in an analogous manner. Therefore, if at least one ofthe two truth values is 1, then at least one of the memory elements P orQ, which was previously initialized to 0, is in the state 1. The truthvalue 1 of the operation “K OR L” is therefore embodied in that at leastone memory element P or Q is in the state 1. However, if both truthvalues are 0, then both memory elements P and Q remain in the state 0.The truth value 0 of the operation “K OR L” is embodied in that bothmemory elements P and Q are in the state 0. The result of the operationhas therefore been stored in the states of the memory elements P and Q.

In a particularly advantageous embodiment of the invention, after thepoles of the memory elements P and Q have been acted upon by the voltagelevels of the variables K and L, at least one of the memory elements Pand Q is acted upon by the read voltage V_(R) thereof. Advantageously, aparallel circuit of the memory elements P and Q is acted upon by avoltage that acts on both memory elements P and Q as read voltage V_(R).In the stated example of the OR operation, both memory elements P and Qare switched between the potential of the read voltage V_(R) and theground potential for this purpose.

It was recognized that this application of the read voltage V_(R) drivesa current pulse through the memory element(s) or through the parallelcircuit, provided a 1 has been stored as the result of the operation inthe states of the memory elements P and Q in the above-described manner.The application of the read voltage V_(R) then transfers at least one ofthe memory elements P and Q from the state 1 into the ON state. With thedesign according to the invention, the memory element becomeslow-impedance as a result, and an easily detectable read current flows.However, if a 0 is stored as the result of the operation in the statesof the memory elements P and Q, and both memory elements are thereforein the state 0, then the application of the read voltage V_(R) does notchange this. Both of the memory elements remain high-impedance. The highread current fails.

Applying the read voltage V_(R) to only one of the memory elements P orQ is sufficient when the truth value of the logic operation that wasperformed has already been defined due to the state that is read out asa result. It is then possible to omit a working cycle for reading outthe second memory element. In the example presented above, if the truthvalue of the operation “K OR L” has been stored in the array, forinstance, in that the memory element P was switched into the state 1,then it is already clear that the truth value of the operation is 1after the readout of the memory element P with the read voltage V_(R)thereof. The memory element Q does not need to be read out any moresince the state thereof does not change anything about the result.However, if the truth value of the logic operation that was performed isnot yet clear after the readout of the first memory element, and thememory element P in the example presented above is in the state 0, thenthe second memory element (Q in this case) must also be read out.

Alternatively or in combination with the application of at least one ofthe memory elements having the read voltage V_(R), in a furtherparticularly advantageous embodiment of the invention, the timecharacteristics of the currents that are driven through the array whenthe voltage levels of the variables K and L are applied to the poles ofthe memory elements P and Q are evaluated to determine the truth valueof the logic operation. In the description of the method for operating amemory element, a stack or a memory matrix, it was already stated thatswitching a memory element transfers it into the ON state for a shorttime period and therefore drives a current pulse through the memoryelement during this time period. Since such pulses are awaited after thevoltage levels of the variables K and L are applied to the poles of thememory elements P and Q, it is advantageously possible to determinewhether at least one memory element in the array was switched.

In the example of the operation “K OR L” presented above, the memoryelement P is switched into the state 1 when the truth value of K isequal to 1. The memory element Q is switched into the state 1 when thetruth value of L is equal to 1. If, when K is applied to P or L isapplied to Q, a current pulse appears in the current driven by thearray, this delivers the information that at least one of the memoryelements P and Q was switched, and the truth value of the operation istherefore equal to 1.

The advantage of this embodiment is that a separate voltage source for aread voltage V_(R) and a working cycle is non-essential for reading theresult out of the array. The result emerges from the array in the formof the current pulse immediately after it forms, and can be processedfurther, e.g. for the calculation of a combined logic function in anadder. The result is nevertheless still stored in the array and can beextracted from the array once more by applying the read voltage V_(R) tothe parallel circuit of the two memory cells P and Q.

In a particularly advantageous embodiment of the invention, memoryelements P and Q according to the invention are selected according toone of the claims directed to a memory element. The memory elementsaccording to the invention offer the decisive advantage, with respect tothe method, that they are low-impedance when, and only when, they havebeen transferred by the read voltage V_(R) from the state 1 into the ONstate. Otherwise they are high-impedance, and therefore parasiticleakage currents are advantageously prevented. This is important inparticular when the intention is to use the method to evaluate a morecomplex logic expression. If many memory elements are disposed in amatrix for this purpose, for example, then, according to the prior art,a large number of paths for leakage currents existed between twoarbitrary space points in this matrix, which were also dependent uponwhich bit patterns were stored in the matrix. The use of memory elementsaccording to the invention eliminates these leakage currents and therebyensures that the method delivers reliable truth values.

In a particularly advantageous embodiment of the invention, a stackaccording to the invention, which comprises the memory elements P and Q,and/or a memory matrix according to the invention is selected as thearray comprising memory elements. It was recognized that nothing aboutthe memory elements, the stack or the memory matrix itself needs to bechanged to upgrade the function thereof from a memory for fixedlyspecified data to a memory for truth values of a logic operation. Thechange is the manner in which the memory elements are acted upon bysignals.

It is therefore possible to reconfigure the same hardware to the runtime of various intended uses. The previous strict separation betweenthe arithmetic-logic unit and the memory of a microprocessor and,therefore, the basic limitation of computing speed by the connectionsystem between arithmetic-logic unit and memory (“von Neumannbottleneck”) is hereby eliminated. By way of an appropriate connectionof a memory matrix, it is also possible to carry out massively parallellogic and, therefore, computer operations, whereby further gains inspeed are possible.

If the method is used to reconfigure a memory matrix entirely or in partinto a microprocessor, then a microprocessor is created, in which thefunctional elements, which are massively present, are free oftransistors, and only a few transistors are required for the peripheralcontrol. According to the previous prior art, one microprocessorcontains several million transistors which take up a lot of space on thechip. In addition, transistors that are made of semiconductors havingdifferent dopings are much more complex to manufacture than memoryelements according to the invention.

The substantially low leakage currents and correspondingly lower powerlosses of the memory elements according to the invention make athree-dimensional memory matrix comprising stacks of memory elementspractical. The limiting factor for the size of such a memory matrix isthe heat dissipation out of the center of this matrix. Since the memoryelements according to the invention produce less heat, the matrix canbecome much larger. If such a matrix is now reconfigured entirely or inpart into a microprocessor using the method according to the inventionfor determining the truth value of a logic operation, then amicroprocessor can be made available for the first time, the verticalexpansion of which is comparable to the horizontal expansion thereof.Random access to any region within the three-dimensional matrix isconstantly available.

In a particularly advantageous embodiment of the invention, the memoryelements P and Q having different polarities are each switched betweenthe voltage level of the variable K and that of the variable L. In thisembodiment, an exclusive OR operation (XOR) of the variables K and L isachieved.

If the variables K and L have the same truth value, then voltage doesnot drop across the memory element P or across the memory element Q.Both memory elements remain in the state 0 in which they wereinitialized at the beginning. If the read voltage V_(R) is now appliedto both memory elements P and Q or a parallel circuit thereof, bothmemory elements remain high-impedance, and a very low current flowsthrough the parallel circuit. However, if the variables K and L havedifferent truth values, the difference of the corresponding voltagelevel is present at the memory element P and, with the opposite sign, atthe memory element Q. Then one of the two memory elements is switchedinto the state 1. If the read voltage V_(R) is now applied, this memoryelement is switched from the state 1 into the ON state. This memoryelement therefore forms a low-impedance path for the current driven bythe read voltage V_(R). An easily detectable read current flows throughthis memory element or through a parallel circuit of both memoryelements P and Q. Alternatively or in combination therewith, when thevoltage levels of K and L are applied simultaneously, the timecharacteristic of the current flowing through the array can beevaluated. If a short current pulse appears therein, then one of thememory cells P or Q was switched into the state 1, and the truth valueof the XOR operation is 1. If such a current pulse does not appear, thenneither of the two cells was switched, and the truth value is 0.

The truth value of the variable K can be inverted to “NOT K” by carryingout an XOR operation with 1 as the truth value of the variable L.Finally, it is therefore possible to also achieve the operation “K ANDL” by switching a further memory element, which was initialized to 0,between the voltage level of the variable L and the voltage level of“NOT K”. The further memory element is switched from the state 0 intothe state 1 only when the two voltage levels are different, i.e. K and Lboth have the truth value 1. A switch from this state into the ON statecan be achieved by applying the read voltage V_(R), thereby enabling aneasily detectable read current to flow.

Any arbitrary logic circuit such as a full adder for addition of threetruth values can comprise the operations OR, AND, NOT and XOR, shownhere, and the universal NOR gate which can also be achieved.

The XOR operation can be used, for example, in convolutional coders fortelecommunications, in cryptographic encoders and dual-rail decoders.

The subject matter of the invention is explained in the following ingreater detail with reference to figures, without the subject matter ofthe invention being limited thereby.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a, 1 b and 1 c show current-voltage characteristic curves of twomemory cells A and B (subfigures 1 a and 1 b) and an embodiment of thememory element according to the invention, which comprises these memorycells A and B (subfigure 1 c).

FIG. 2 Shows the temporal characteristics of voltage pulses that areapplied to the memory element shown in FIG. 1 c for writing and reading,including the particular response of the memory element.

FIG. 3 Shows the effect of a variability of 10% in the characteristicvalues of the memory cells A and B on the usable bandwidth of the writeand read voltages.

FIG. 4 Shows an exemplary embodiment of the memory element according tothe invention, in which the current-voltage characteristic curve wassymmetrized byway of a further resistor R connected in series with thememory cells A and B.

FIG. 5 Shows an exemplary embodiment of the memory matrix according tothe invention.

FIGS. 6 a and 6 b show a comparison of the maximum possible number ofmemory elements in a memory matrix for a specified signal level betweenthe readout of a 0 and the readout of a 1 between a memory matrixaccording to the prior art (subfigure 6 a) and a memory matrix(subfigure 6 b) according to the invention.

FIG. 7 Shows an exemplary embodiment of the method according to theinvention for determining the truth value of a logical OR operation:initialization (subfigure 7 a), storage of the truth value (subfigure 7b), readout of the truth value (subfigure 7 c).

FIGS. 8 a, 8 b and 8 c shows an exemplary embodiment of the methodaccording to the invention for determining the truth value of a logicalOR operation, in which a stack of memory elements according to theinvention is used: initialization (subfigure 8 a), storage of the truthvalue (subfigure 8 b), readout of the truth value (subfigure 8 c).

FIGS. 9 a, 9 b and 9 c shows an exemplary embodiment of the methodaccording to the invention for determining the truth value of a logicalXOR operation, which uses a memory matrix according to the invention:initialization (subfigure 9 a), storage of the truth value (subfigure 9b), readout of the truth value (subfigure 9 c).

FIGS. 10 a, 10 b and 10 c shows an exemplary embodiment of the methodaccording to the invention for determining the truth value of a logicalXOR operation, which uses a stack of memory elements according to theinvention: initialization (subfigure 10 a), storage of the truth value(subfigure 10 b), readout of the truth value (subfigure 10 c).

FIG. 11 Shows an exemplary embodiment of a resistive working memory(RRAM) according to the invention, in a perspective view.

FIG. 12 Shows an illustration of the problem of parasitic currents in amemory matrix.

FIG. 13 Shows an exemplary embodiment of the 2/3 voltage pattern thatprevents the influencing of non-addressed memory elements duringwriting.

FIG. 14 Shows an measured I-V characteristic curve of a memory elementaccording to the invention.

FIG. 15 Shows a sequence of voltage pulses, presented as an example,which a memory element in a memory matrix undergoes, and currents driventhrough the memory element. Voltages and currents are shown for theaddressed memory element and for a non-addressed memory element.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 a and 1 b show the current (I)/voltage (V) characteristic curvesof two identical memory cells A and B in random units, and theparticular circuit diagrams in which the particular characteristiccurves are obtained. With regard to the voltage V that is applied, thepolarity of the memory cell B is reversed with respect to the memorycell A. The memory cells A and B are designed to be bipolar switching.The voltage V_(A) or V_(B), which drops across the memory cells A and B,is identical to the applied voltage V_(in), in each case.

The I/V characteristic curve shown in FIG. 1 a for the memory cell Astarts at the state A0 with high electrical resistance (a). When thevoltage dropping at the memory cell A reaches the positive switchingthreshold, which is 1 (b) in this case, the memory cell A is transferredinto the state A1, and the electrical resistance thereof drops. Theconductivity increases abruptly, and the slope of the I/V characteristiccurve increases with changes in the voltage that now follow (c). Thisapplies not only when the voltage is increased further, but also when itdrops back below the positive switching threshold or even when the signchanges with passage through the origin. The memory cell A is switchedback into the state A0 when the voltage reaches the negative switchingthreshold, which is −1 (d) in this case. The slope of the I/Vcharacteristic curve abruptly takes on the original value once more forfurther changes to the voltage V, regardless of whether this changetakes place in the negative direction or in the positive direction (e).

The I/V characteristic curve shown in FIG. 1 b for the oppositely poledmemory cell B starts at the state B1 having low electrical resistance.The slope of the characteristic curve is high (a). If the positiveswitching threshold, which is 1 (b) in this case, is reached, then thememory cell B is switched into the state B0. The resistance increases.The slope of the I/V characteristic curve decreases abruptly for thesubsequent changes in the voltage V, regardless of whether the voltageis further increased or reduced (c). This lesser slope is retained evenwhen the sign of the voltage V changes with passage through the origin.The memory cell B is switched back into the state B1 when the voltagereaches the negative switching threshold, which is −1 (d) in this case.The resistance decreases and the slope of the I/V characteristic curveincreases abruptly, regardless of whether the voltage V is subsequentlychanged in the direction of the negative V axis or the positive V axis.

FIG. 1 c shows the I/V characteristic curve for an exemplary embodimentof the memory element according to the invention. This memory elementcomprises the identical, antiserially connected, resistive memory cells,the behavior of which as individual cells was studied in FIGS. 1 a and 1b including a related description. FIG. 1 c also shows the associatedwiring diagram, in which the depicted characteristic curve is obtained.By way of the embodiment according to the invention of the memoryelement as a voltage divider, the applied voltage V is now divided intotwo voltages V_(A) and V_(B), which drop across the memory cells A andB. The greater voltage drops across the memory cell having the higherresistance.

The characteristic curve starts with the combination of the states A0and B1, i.e. in the state 1 of the memory element (a). At a firstpositive switching threshold, which is 1 (b) in this case, whichcorresponds to the minimally required read voltage V_(R), the memorycell A is switched into the state A1. Since both memory cells now havelow electrical resistance, the total resistance of the series circuit isabruptly reduced and the slope of the I/V characteristic curve increasesfor the further slope of the voltage V (c). The transfer of the memorycell A into the state A1 is preferred over the transfer of the memorycell B into the state B0 because the memory cell A in the state A0 hasthe higher resistance, and therefore, in the voltage divider, thegreater portion of the applied voltage V drops across the memory cell A.The memory cell B switches into the state B0 when the voltage V reachesa second positive threshold, which is 2 (d) in this case, whichcorresponds to the minimally required write voltage V. The totalresistance of the series circuit is now high once more, and the slope ofthe I/V characteristic curve decreases abruptly once more for futurechanges in the voltage V (e). The memory element is in the state 0.Analogously, there are two negative switching thresholds. At the firstnegative switching threshold, which is −1 (f) in this case, whichcorresponds to the minimally required read voltage V_(R) on the negativeaxis, the memory cell B is switched back into the state B1. Thisswitchover is preferred over the transfer of the memory cell A into thestate A0 since the memory cell B in the state B0 has the greaterresistance and, in the voltage divider, the largest portion of theapplied voltage V_(in) drops across the memory cell B. Since both memorycells now have low resistance once more, total resistance is reduced;the conductivity and, therefore, the slope of the I/V characteristiccurve increase abruptly (g). At a second negative switching threshold(which is −2 in this case), which corresponds to the minimally requiredwrite voltage V₁, memory cell A is switched into the state A0 (h). Thetotal resistance of the series circuit increases, and the conductivityand, therefore the slope, of the I/V characteristic curve decreaseabruptly (i). The memory element, as a whole, returns to the state 1.

The region between the two positive switching thresholds, or between thetwo negative switching thresholds, forms the read window. When voltagesare in this range, the memory element can be read out. In practicalapplication, the read window is usually not fully utilized, but rather asafety margin of approximately 10% from the upper limit and from thelower limit is maintained in order to account for possible variabilitiesof the switching thresholds in a matrix comprising many nominallyidentical memory elements.

FIG. 2 shows, for the exemplary embodiment of the memory elementaccording to the invention shown in FIG. 1 b, the temporalcharacteristics of pulses for various operations and the resultingtemporal characteristics of the current flowing through the memoryelement. The state in which the memory element is located at which timeis indicated on the lower edge of FIG. 2.

Starting at the state 0, first a pulse having the read voltage V_(R),which is 1 in this case, is applied (a). Since state 0 is coded in thestate combination A1 and B0, this pulse does not change anything aboutthe configuration of the memory cells. Therefore, this pulse does notcause the current to change, either. A 0 has been read out.

Next, a pulse having the write voltage V₁, in this case −2.5, is applied(b). The memory cell A is switched into the state A0, and the memorycell B is switched into the state B1. This is exhibited by a brief spikein the current through the memory element. Once the switchover iscomplete, the memory element is in the state 1, and the current takes onthe original value once more. The spike delivers the information thatthe memory element was in the state 0 before the writing, and that theswitchover into the state 1 was successful.

A subsequently applied pulse having the read voltage V_(R) (C) switchesthe memory cell A into the state A1. Since both memory cells are now inthe state of low resistance, an easily detectable read current flows forthe duration of the pulse (state “ON”). A 1 has been read out.

Since the memory element has left the state 1 due to the readout, it isnext written back into the memory element by a new pulse having thewrite voltage V₁ (d). A brief spike is exhibited in the current oncemore, since the memory cell A is switched from the state A1 back intothe state A0.

Next, a pulse having the write voltage V₀, in this case +2.5, is applied(e). Analogous to the writing of a 1, a brief spike occurs in thecurrent (with reverse polarity) during the switchover from A0 to A1 andfrom B1 to B0.

A subsequent pulse having the read voltage V_(R) (f) does not changeanything about the configuration of the memory cells A and B andtherefore likewise does not result in a change of the current throughthe memory element. A0 has been read out.

FIG. 3 illustrates a worst-case estimate regarding which range istolerable in the switching voltages and resistance values of theindividual memory cells. This is relevant in particular for memorymatrices comprising a very large number of nominally identical memoryelements.

FIG. 3 shows, in a section from the I/V characteristic curve of theexemplary embodiment shown in FIG. 1 b, how a variability in theswitching voltages and resistance values of the memory cells A and B ofup to ±10% propagates onto the variability of the first and the secondpositive switching threshold and the destruction threshold of the memoryelement. Ranges are indicated within which the first positive switchingthreshold (a), the second positive switching threshold (b) and thedestruction threshold (c) can vary due to the assumed variability of±10% in the parameters of the memory cells. The windows that remain areindicated below the V axis, with consideration for these variabilities,for the highest permissible voltage (d) present at a non-addressedmemory element, for the read voltage V_(R) (e) and for the write voltageV₀ (f). Since sufficiently large and non-overlapping windows remain forall three parameters, a variability of up to ±10% in the characteristicvalues of the individual memory cells is definitely tolerable.

In FIG. 4, an exemplary embodiment of the memory element according tothe invention is shown comprising a further resistor R which isconnected in series with the memory cells A and B. The I/Vcharacteristic curve, including the switching thresholds, corresponds tothe characteristic curve shown in FIG. 1 c. Even when the characteristiccurves of the memory cells A and B are not symmetrical about the origin,unlike the depiction in FIGS. 1 a and 1 b, a characteristic curve thatis symmetrical about the origin can still be achieved for the memoryelement as a whole by way of the further resistor provided according tothe invention. By way of the voltage V_(R) dropping thereacross, thefurther resistor R in the voltage divider causes identical voltagesV_(A) and V_(B) to drop across the memory cells A and B in thecombination of the states A1 and B1. In the exemplary embodiment, theresistance value of R is seven times as great as the resistance valuesof the memory cells A and B in the states A1 and B1.

The more symmetrical the characteristic curve is about the origin, thegreater the read window is for the read voltage V_(R).

FIG. 5 shows an illustration of an exemplary embodiment of a memorymatrix according to the invention. This memory matrix does not containany active switching elements which can be controlled independently ofthe current through the word lines W or the bit lines B. The word linesW extend vertically and the bit lines B extend horizontally. A memoryelement S according to the invention is connected between a word line Wand a bit line B in each case. Each word line W can be acted upon by avoltage, by way of a column decoder CD, by way of a transistor TCassigned thereto. Every bit line B can be acted upon by a voltage by aline decoder RD, by way of a transistor TR assigned thereto. Every bitline B is connected by way of a pull-up resistor SR to the supplyvoltage V_(DD). Provided a bit line B is acted upon by a voltage by wayof the transistor TR assigned thereto, this transistor alsosimultaneously establishes a connection between this bit line B and avoltmeter M which delivers an output voltage V_(out).

At any given time, only one word line W and one bit line B arecontrolled by the decoders CD and RD. Therefore, precisely that memoryelement S connected between this word line W and this bit line B isaddressed. The voltages applied to the word line W and the bit line Bare selected such that, in all, the read voltage V_(R) is present at theaddressed memory element S. If this memory element S is in the state 0,then only that voltage applied to the controlled bit line B induces acurrent flow through the sensor resistor SR of this bit line B and,therefore, a voltage drop at this sensor resistor SR. This voltage dropis registered by the voltmeter M. However, if the memory element S is inthe state 1, it is transferred, as a whole, by way of the read voltageV_(R), into the ON state with low resistance. The read current thatflows through the memory element as a result induces an additionalvoltage drop at the sensor resistor SR assigned to the bit line B, whichis registered by the voltmeter M.

However, it is entirely possible for several, or even all, word lines orbit lines to be controlled simultaneously. As a result, the informationcan be transferred into and out of the memory matrix in blocks, therebyincreasing the data throughput.

Parasitic currents through non-addressed memory elements S areadvantageously minimized by way of the design of the memory elementsaccording to the invention. They cannot be completely eliminated,however. Every parasitic current likewise flows across the sensorresistor SR and therefore delivers an additional contribution to thevoltage drop across this sensor resistor, which is registered by thevoltmeter M. Therefore, there are a finite number of memory elements Sat which the voltages registered by the voltmeter M upon readout of a 0or a 1 from the addressed memory element S cannot be reliablydifferentiated from one another.

FIG. 6 a shows, for a memory matrix comprising resistive memory elementsaccording to the prior art, which have only one memory cell, and FIG. 6b shows, for the memory matrix according to the invention, the ratioAVIV of the voltage step between the voltages V_(out) between thevoltages V_(out) registered by the voltmeter M upon the readout of a 0and the readout of a 1, and the operating voltage of the memory matrixdepending on the number n of memory elements in the memory matrix. Theratio ΔV required for a technically safe readout and the maximum numberof memory elements the memory matrix is allowed to have to ensure thatthis requirement is still met depends on the complexity of the design ofthe voltmeter M.

Even if a voltage step ΔV of only 10% of the operating voltage isrequired, which does not pose a great challenge given the current stateof the art of analog electronics, the memory matrix according to theprior art reaches this limit, which is shown in FIGS. 6 a and 6 b as adotted line, with a size of only 8 memory elements. In contrast, in thememory matrix according to the invention, the voltage step is still farabove the threshold of 10%, even when 100,000 memory elements arepresent. The memory matrix according to the invention is thereforewithin the dimensions that are relevant for data processing.

For a memory matrix of 512×512 memory elements, a voltage step of 86.7%of the supply voltage can be achieved if the memory elements typicallyhave a resistance value of 10⁸Ω in the state of high electricalresistance and have a resistance value of 2 kΩ in the state of lowelectrical resistance.

FIG. 7 illustrates an exemplary embodiment of the method according tothe invention for determining the truth value of a logic operation. Anarray of two memory elements P and Q according to the invention areused. The memory element P has poles P₁ and P₂, which are accessible fora connection. The memory element Q has poles Q₁ and Q₂. The shading ofeach of the memory elements P and Q indicates the state in which thememory element is located. A dark shading corresponds to the state 0, alight shading corresponds to the state 1, and a light color with hashmarks corresponds to the ON state.

The assignment of the poles P₁ and P₂ or Q₁ and Q₂ is selected, withoutloss of generality, such that a write voltage V₀, which increases thepotential at pole P₁ relative to the potential at pole P₂, switches thememory element P from the state 1 into the state 0. In an analogousmanner, the write voltage V₀, which increases the potential at Q₁relative to the potential at pole Q₂, switches the memory element Q fromthe state 1 into the state 0.

FIG. 7 a shows how the array is initialized. Both memory elements P andQ are initialized into the state 0 by bringing the poles P₁ and Q₁thereof to the potential V, and the poles P₂ and Q₂ thereof to theground potential GND. The potential at the poles P₁ and Q₁ is thereforeincreased relative to the potential at the poles P₂ and Q₂. A potentialdifference having this polarity switches both memory cells P and Q intothe state 0.

FIG. 7 b shows how the truth value of the logic operation of twovariables K and L is subsequently stored in the array. In this example,K has the truth value 0 to which the potential V is assigned as thevoltage level. L has the truth value 1 to which the ground potential GNDis assigned as the voltage level. The potential V is present at thepoles P₂ and Q₂. Voltage does not drop across the memory element P sincethe same potential is present at the two poles P₁ and P₂. The memoryelement P remains in the state 0. In contrast, the write voltage V dropsacross the memory element Q from Q₂ to Q₁ relative to ground. As aresult, the memory element Q is switched into the state 1. The truthvalue 1 of the operation “K OR L” is now embodied in the states 0 and 1of the memory elements P and Q, which are now present.

FIG. 7 c shows how this truth value is subsequently read out of thearray. A read voltage V_(R) is applied at the poles P₁ and Q₁ relativeto the poles P₂ and Q₂ which are at ground potential GND. This readvoltage V_(R) lies within the positive read window of the memoryelements P and Q (see FIG. 1 c). This does not change anything about thestate of the memory element P which is in the state 0. Memory element Q,however, which is in the state 0, is switched into the ON state. Aneasily detectable read current flows through the memory element Q and,therefore, through the parallel circuit. This read current indicatesthat the truth value stored in the array was 1.

FIG. 8 shows a further embodiment in which the truth value of the logicoperation “K OR L” is determined. The difference from the embodimentshown in FIG. 7 is that, instead of two adjacently disposed memoryelements P and Q, a stack of these memory elements P and Q according tothe invention is used. Reference characters that are also used in FIG. 7label parts that act identically to the corresponding parts shown inFIG. 7.

FIG. 8 a shows how the two memory elements P and Q are initialized. Tothis end, the potential V is applied to the poles P₁ and Q₁. The polesP₂ and Q₂ are connected by way of an electrical contact O which is actedupon by the ground potential GND. The voltage V drops across the memoryelement P as well as across the memory element Q and, in fact, from P₁to P₂ and from Q₁ to Q₂. It therefore acts as write voltage V₀ on thememory element P and on the memory element Q. Both memory cells P and Qare therefore initialized into the state 0.

FIG. 8 b shows how the truth value of the operation “K OR L” isdetermined in this embodiment. In this example, K has the truth value 1,to which the ground potential GND is assigned as the voltage level. Lhas the truth value 0, to which the potential V is assigned as thevoltage level. The voltage V drops across the memory element P from P₂to P₁, and therefore this memory element is switched into the state 1.There is no voltage drop across the memory element Q. The state thereofremains unchanged at 0. The truth value 1 of the operation “K OR L” isnow embodied in the states 1 and 0 of the memory elements P and Q, whichare now present.

FIG. 8 c shows how this result is read out of the array. Both memoryelements P and Q are acted upon by a read voltage V_(R) which lieswithin the positive read window of the memory elements P and Q (see FIG.1 c). To this end, the ground potential GND is applied to the contact Oby way of which the memory elements P and Q are interconnected. Thepoles P₂ and Q₂ are therefore at ground potential GND. The poles P₁ andQ₁, however, are at the potential V_(R). The voltage drop V_(R) from P₁to P₂ transfers the memory element P, which has been switched into thestate 1, into the ON state and makes it low-impedance. An easilydetectable read current flows through this memory element. By way of theresistance R_(PD) which is switched to ground, this read current inducesa voltage drop which can be detected using the operational amplifiershown.

FIG. 9 shows an exemplary embodiment of the method according to theinvention for determining the truth value of a logic operation of twovariables K and L, which uses a memory matrix according to the inventionas the array of memory elements. The memory matrix comprises two wordlines, Word1 and Word2, and bit lines Bit1 and Bit2 which intersect theword lines. The intersecting word lines and bit lines are interconnectedat the intersections by four memory elements P, Q, R and S.

FIG. 9 a shows how all four memory elements P, Q, R and S areinitialized into the state 0. A voltage V, which acts as write voltageV₀ on all four memory elements, is applied to both word lines, whileboth bit lines are connected to the ground potential.

FIG. 9 b shows how the truth value of the operation “K XOR L” is storedin the memory matrix. In this example, K has the truth value 1 to whichthe voltage V is assigned as the voltage level. L has the truth value 0to which the ground potential (GND) is assigned as the voltage level.The word line Word1 and the bit line Bit2 are now acted upon by thevoltage level of K (V), which is present at the pole P₁ of the memoryelement P and at the pole Q₂ of the memory element Q. The word lineWord2 and the bit line Bit1 are now acted upon by the voltage level of L(GND), which is present at the pole P₂ of the memory element P and atthe pole Q₁ of the memory element Q.

The voltage drop V across the memory element P from P₁ to P₂ is the sameas before upon initialization. It therefore acts on the memory element Pas write voltage V. The state of the memory element P therefore remainsunchanged, at 0. The memory element Q, however, is acted upon by anoppositely poled voltage drop from Q₂ to Q₁. This voltage drop acts onthe write element Q as write voltage V₁. As a result, the memory elementQ is switched into the state 1. The truth value 1 of the operation “KXOR L” is now embodied in the states 0 and 1 of the memory elements Pand Q, which are now present.

FIG. 9 c shows how this truth value is read out of the memory matrix.Both word lines are acted upon by a read voltage V_(R) which lies withinthe positive read window of the memory elements P and Q. This readvoltage V_(R) further switches the memory element Q, which is in thestate 1, into the ON state. The memory element Q is thereforelow-impedance.

The current flowing from both bit lines through the resistor R_(PD) toground causes a voltage drop at this resistor, which is measured usingthe operational amplifier shown. There is a low-impedance path for thecurrent through the memory element Q which is in the ON state.Therefore, an easily detectable read current, which exhibits the truthvalue 1, flows.

The memory elements R and S do not have a function in this example. Whenthe truth value “K XOR L” is stored in the memory matrix, L is presentat both poles of the memory element R, and K is present at both poles ofthe memory element S. After the initialization to 0, the memory elementsR and S no longer undergo a voltage drop that could suffice for aswitchover into the state 1. Now, if L is applied instead of K to theword line Word1, and K instead of L is applied to the word line Word2or, instead, if K is applied to the bit line Bit1 instead of L, and L isapplied to the bit line Bit2 instead of K, the memory elements P and Qstop functioning and storage of the truth value is taken over by thememory elements R and S. This can be used to continue working with theremaining memory elements R and S if one of the memory elements P or Qshould fail.

FIG. 10 shows a further exemplary embodiment for determining the truthvalue of the logic operation “K XOR L”. Analogous to the exemplaryembodiment shown in FIG. 8, this exemplary embodiment shows a stackaccording to the invention of two memory elements P and Q as an array.

FIG. 10 a shows how both memory elements P and Q are initialized intothe state 0. The electrical contact 0, which connects the pole P₂ of thememory element P to the pole Q₁ of the memory element Q, is acted uponby the ground potential (GND). P₁ is now brought to the potential V, andQ₂ is brought to the potential −V. In the memory cell P and in thememory cell Q, the potential therefore increases from pole P₂ or Q₂toward contact P₁ or Q₁, respectively, by the magnitude V. This acts onboth memory elements P and Q as write voltage V₀ which initializes bothmemory elements into the state 0.

FIG. 10 b shows how the truth value of the operation “K XOR L” is storedin the stack. P₁ and Q₂ are each acted upon by the voltage level of thevariable K. In this example, K has the truth value 1 to which thevoltage V is assigned as the voltage level. The contact 0 is acted uponby the voltage level of the variable L. In this example, L has the truthvalue 0 to which the ground potential (GND) is assigned as the voltagelevel.

The potential increases from P₂ to P₁ by the magnitude V, as in theinitialization. The write voltage V₀ still acts on the memory element Pas before, and therefore P remains in the state 0. A voltage which hasthe same magnitude but is oppositely poled drops across the memoryelement Q. The potential now increases from Q₁ to Q₂ by the magnitude V.This is equivalent to a voltage drop from Q₂ to Q₁ by the same amountand therefore acts on the memory element Q as write voltage V₁. Q isswitched into the state 1. The truth value 1 of the operation “K XOR L”is now coded in the states 0 and 1 of the memory elements P and Q, whichare now present.

FIG. 10 c shows how this truth value is read out of the stack. Thememory element P is acted upon by a potential increase by the amountV_(R), which lies in the range of the positive read window, from P₂ toP₁. This changes nothing about P being in the state 0. The memoryelement Q is acted upon by a potential increase by the amount V_(R) fromQ₂ to Q₁ by the application of −V_(R) to Q₂. Since the memory element Qis in the state 1, it is switched further into the ON state and istherefore low-impedance. An easily detectable read current thereforeflows through the memory element Q, which can be measured using theoperational amplifier by way of the voltage drop induced at the resistorR_(PD) relative to ground. The read current embodies the read-out truthvalue 1 of the operation.

The assignment of the voltage levels to the truth values of thevariables K and L shown in FIGS. 9 and 10 is reversed relative to theFIGS. 7 and 8. In FIGS. 7 and 8, the potential V is assigned to thetruth value 0, and the ground potential GND is assigned to the truthvalue 1. Advantageously, the result of this is that it is only necessaryto work with positive voltages and, therefore, only positive voltagesources.

FIG. 11 shows an exemplary embodiment of a resistive working memory(RRAM) 10 according to the invention, in a perspective view. The workingmemory 10 contains a memory matrix 12 according to the invention havingintersecting word lines and bit lines. The word lines 14 arestrip-shaped and were manufactured at regular intervals relative to oneanother on a substrate which is not shown in FIG. 11. The bit lines 16,which are also strip-shaped, were manufactured at regular intervalsrelative to one another on a second plane which is located at aspecified distance from the first plane in which the word lines 14 arelocated. In the memory elements 22 located at the intersections betweenthe word lines 14 and the bit lines 16, the word lines 14 are the firstelectrode 18, and the bit lines are the second electrode 20. Each of thememory elements 22 contains a stack of layers 26, 28 and 30 between theelectrodes 18 and 20 thereof.

In one embodiment of the invention, the first electrode 18 is inert(such as platinum). The first layer 26 on the first electrode 18 is afirst layer of an active material (such as germanium selenide GeSe). Thesecond layer 28 on the first layer 26 is an electrochemically activeelectrode (such as copper). The third layer 30 on the second layer 28 isa second layer of an active material (such as a further layer made ofgermanium selenide Ge-Se). The second electrode 20 on the third layer isalso an inert electrode (such as platinum).

In a further embodiment of the invention a different sequence of layersis provided. The first electrode 18 is an electrochemically activeelectrode (such as copper). The first layer 26 on the first electrode 18is a first layer of an active material (such as germanium selenide). Thesecond electrode 28 on the first layer 26 is also an inert electrode(such as platinum). The third layer 30 on the second layer 28 is asecond layer of an active material (such as germanium selenide). Thesecond electrode 20 on the third layer is an electrochemically activeelectrode (such as copper).

In both embodiments, the layer stack in the resistive memory elements 22can be seen in the equivalent circuit diagram as a series circuit 32which comprises at least two functionally identical memory cells 34, 36,as shown on the right in FIG. 1 c. These two resistive memory cells 34and 36 are connected in series, but are oriented electricallyantiparallel relative to one another. They are antiserially connected.The first memory cell 34 comprises the first electrode 18, the firstlayer 26 and the second layer 28. The second memory cell 36 comprisesthe second layer 28, the third layer 30 and the second electrode 20.Every memory element 22 is a passive bipolar switching, resistive memoryelement 38 that contains no further active switching elements aside fromthe memory cells.

Every memory element 22 is always in the state of high electricalresistance if it is acted upon by no voltage at all, or if it is actedupon by a write voltage.

The memory matrix is preferably embodied as a hybrid solution of CMOStechnology and nanoelectronics. To this end, the nanoelectric memorymatrix is placed onto a CMOS logic circuit. With regard to the surfaceusage and the scalability, the passive memory matrix comprisingintersecting word lines and bit lines is the most effective way toachieve a nanoelectric memory. Every intersection 24 of a word line 14and a bit line 16 forms a memory element 22 having minimal cell size 4F², in which F is the minimal feature size. The absence of activeswitching elements, with the exception of the memory elementsthemselves, makes the memory matrix entirely passive.

FIG. 12 illustrates the problem of parasitic currents in a passivememory matrix, which have prompted the present invention. Every wordline 14 is connected directly to every bit line 16 by way of a singleresistive memory element 22. Within the memory matrix, however this wordline and this bit line are connected by way of various parasitic currentpaths 58, 60, each of which contains at least one further word lineand/or bit line and a large number of further resistive memory elements.By using memory elements according to the prior art, the voltage stepbetween the states 0 and 1 of the addressed memory element that can beachieved upon application of the read voltage V_(R) decreases rapidly asthe size of the memory matrix increases, and is highly dependent uponthe bit pattern written into the memory matrix. In a worst-casescenario, the voltage step is 10% of the supply voltage in an arrayhaving only 8×8 memory elements. A low voltage step and bit patterndependence require large amplifiers for detecting the voltage step,limit the scope of application of the memory matrix to low numbers ofmemory elements and likewise limit the access time. The static powerloss due to the parasitic current paths that occur during reading andduring writing is an additional problem.

FIG. 13 shows an exemplary embodiment of the 2/3 voltage pattern whichprevents influencing of non-addressed memory elements when informationis written into a memory element 22 of a memory matrix. The full writevoltage V_(wr) drops only across the addressed memory element. Thevoltage drop across all other memory elements is limited to 1/3 V_(wr).

FIG. 14 shows the I/V characteristic curve of a memory element accordingto the invention. It is comparable to the characteristic curve in FIG. 1c. In contrast to FIG. 1 c, it is not the calculated characteristiccurve of an ideal memory element, but rather the measured characteristiccurve of an actually embodied memory element made of germanium selenide.

At the beginning of the measurement (range C1), the memory cell A of thememory element is in the state A0, and the memory cell B is in the stateB1. Due to the series circuit, the total resistance is high. Almost allof the voltage drops across the memory cell A until the first positiveswitching threshold V_(th), is reached and the memory cell A switchesinto the state A1 with low resistance. Since the memory cell B remainsin the state B1 and therefore likewise has low resistance, the totalresistance of the memory element is low in the range C2. If the voltagereaches the second positive switching threshold V_(th,2), the memorycell B switches into the state B0 with high resistance. The totalresistance of the memory element is therefore high once more in therange C3. If the voltage is now reduced toward zero, the memory cell Aremains in the state A1 and the memory cell B remains in the state B0(range C4). Initially nothing changes even when the voltage becomesnegative (range C5). The memory cell B, across which almost all of thevoltage drops, switches into the state B1 when the first negativeswitching threshold −V_(th)is reached. Since the memory cell A remainsin the state A1, the total resistance of the memory element becomes low(range C6). If the voltage becomes further negative and the secondnegative switching threshold is reached, the memory cell A is switchedinto the state A0, and the total resistance of the memory element ishigh once more (ranges C7 and C8).

FIG. 15 shows a sequence of voltage pulses, as an example, with which amemory element according to the invention in a memory matrix accordingto the invention can be acted upon, and the currents driven by thesevoltage pulses through the memory element (i). Also shown are thoseparasitic voltages that are induced by the voltage pulses on anon-addressed memory element of the memory matrix, and the parasiticcurrents that are driven by these parasitic voltages through thenon-addressed memory element (ii). In FIG. 14, V_(th,1) is the minimummagnitude of voltage that is required to switchover the first memorycell A of the memory element. V_(th,1) is therefore the minimum for theread voltage V_(R). V_(th,2) is the magnitude of voltage that isrequired to also switchover the second memory cell B of the memoryelement. To switch between the states 0 and 1 of the memory element inall, both memory cells A and B must be switched. In FIG. 14, a writevoltage V₀>V_(th,2) is required to switch into the state 0, and a writevoltage V₁<−V_(th,2) is required to switch into the state 1.

Starting at the state 0 of the addressed memory element, the memoryelement is read out (a), transferred into the state 1 (b), and read out(c), the 1 is written once more (d), the memory element is transferredinto the state 0 (e), and finally readout takes place (f). Duringreadout, a relevant read current flows only if the memory element waspreviously in the state 1. The voltage drop at the non-addressed memoryelements is too low to be capable of switching one of the memory cells Aor B. The state of all non-addressed memory elements therefore remainsunchanged (g).

The invention also relates to a method for writing information into aplurality of the aforementioned bipolar passively switching, resistivememory elements. In this method the following steps are carried out:

-   -   The cells are acted upon by a write voltage pulse having a first        polarity in order to switch them into a first state, and    -   next, the cells are acted upon by a write voltage pulse having        the same but opposite polarity.        The voltage of each of the write pulses is greater, with regard        to magnitude, than the threshold value V_(th,2), which is        required to switch both memory cells A and B of the memory        element.        The invention also relates to a method for reading out        information stored in a plurality of bipolar resistively        switching memory elements, in particular bipolar resistively        switching memory elements according to the invention. In this        method the following steps are carried out:    -   The memory elements are acted upon by a write pulse having a        first polarity, which switches the memory elements into a first        state, and    -   next, one of the memory elements is acted upon by a read        voltage, and the read current induced as a result is measured.        The voltage of the write pulse is greater, with regard to        magnitude, than the threshold value V_(th,2) which is required        to switch both memory cells A and B of the memory element. The        read voltage is lower than V_(th,2). Advantageously it is        greater than V_(th,1).

1.-36. (canceled)
 37. The method according to claim 47, wherein at least one of the two voltage levels is at least as great, with regard to magnitude, as the write voltages V₀ and V₁ of the memory elements P and Q.
 38. The method according to claim 47, wherein upon application of a read voltage V_(R), the magnitude of which is smaller than the write voltages V₀ and V₁, the two states 0 and 1 of the memory elements P and Q become manifest in different electrical resistance values of the memory elements P and Q.
 39. The method according to claim 47, wherein the memory elements P and Q have at least a first stable state 0 and a second stable state 1 which, by applying a first write voltage can be transferred into the state 0 and, by applying a second write voltage, can be transferred into the state 1, wherein, upon application of a read voltage, the amount of which is smaller than the write voltages, the two states 0 and 1 are manifested in different electrical resistance values of the memory element, wherein the memory elements comprise a series circuit of at least two memory cells A and B having at least two memory cells A and B which have, respectively, a stable state A0 and B) having higher electrical resistance, and a stable state A1 and B1 having lower electrical resistance.
 40. The method according to claim 38, wherein at least one of the memory elements P or Q is acted upon by the read voltage V_(R) thereof.
 41. The method according to claim 47, wherein after application of the voltage levels of variables K and L to the poles of the memory elements P and Q, a parallel circuit of the memory elements P and Q is acted upon by a voltage that acts on both memory elements P and Q as read voltage V_(R).
 42. The method according to claim 47, wherein the temporal characteristics of the currents which are driven through the array upon application of voltage levels of variables K and L to the poles of the memory elements P and Q are evaluated to determine the truth value of the logic operation.
 43. The method according to claim 47, wherein memory elements P and Q having nominally identical write voltages V₀, V₁ and read voltages V_(R) are selected.
 44. The method according to claim 47 wherein a stack comprising memory elements P and Q are directed to a stack and/or a memory matrix directed to a memory matrix is selected as the array comprising memory elements.
 45. The method according to claim 47, wherein the memory elements P and Q have different polarities are each switched between the voltage level of the variable K and that of the variable L.
 46. The method according to claim 47, wherein both memory elements P and Q are initialized in the defined state before they are acted upon by the voltage levels of the variables K and L.
 47. A method for determining the truth value of a logic operation of two variables K and L in an array comprising at least two memory elements P and Q each having at least one stable state 0 and one stable state 1, which can each be transferred into the state 0 by applying a first write voltage V₀, and into the state 1 by applying a second write voltage V₁, wherein the variables K and L are provided in the form of two voltage levels assigned to the truth values 0 and 1, wherein the magnitude of the difference between the two voltage levels is at least as great as the write voltages V₀ and V₁ of the memory elements P and Q, at least one of the two poles P₁, P₂ of the memory element P is acted upon by the voltage level of the variable K, and at least one of the two poles Q₁, Q₂ of the memory element Q is acted upon by the voltage level of the variable L, wherein memory elements P and Q are selected, which each contain a series of at least two memory cells A and B, which have, respectively, a stable state A0 and B0 having higher electrical resistance, and a stable state A1 and B1 having lower electrical resistance, wherein, in each of the two memory elements P and Q, the state 0 is coded in the combination of states A0 and B1, and the state 1 is coded in the combination of states A1 and B0. 